Concurrent Multithread (CMT) Processors contain multiple hardware thread units, each multithread processor can execute a program simultaneously. Access of a Translation Lookaside Buffer (TLB) may be required for many applications, e.g. digital signal processing (DSP). The TLB can translate addresses from virtual to real for every instruction and data memory access. Software programs can have program modules that operate at different levels of priority. An operation system may be required to preempt one program module in order to execute another program module of higher priority.
Limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the present application with reference to the drawings.